2008   2007   2006   2005   2004   2003   2002   2001   2000  
 
2008
JOURNALS
-- V. Ferentinos, G. Lafruit, M. Milia, J. Bormans, F. Catthoor, T. Stouraitis, Optimized memory requirements for wavelet-based scalable multimedia codecs, accepted for publication in the Journal of Embedded Computing.
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2007
CONFERENCES
-- D. Gkrimpas, V. Paliouras, On the complexity of joint demodulation and decoding, accepted for presentation, to appear in the Proceedings of the Proceedings of the IEEE Workshop on Signal Processing System Implementation, SiPS'2007, 2007.
-- V. Ferentinos, B. Geelen, F. Catthoor, G. Lafruit, T. Stouraitis, R. Lauwereins, D. Verkest, Adaptive mapping to resource availability for dynamic wavelet-based applications, accepted for presentation, to appear in the Proceedings of the of ESTIMedia'2007, Salzburg, Austria, Oct. 2007.
-- C. Basetas, I. Kouretas, V. Paliouras, Low-power digital filtering based on the logarithmic number system, Proceedings of PATMOS'2007, LNCS 4644, Springer, pp. 546-555, 2007.
-- E. Fotopoulou, T. Stouraitis, Analysis and design of a WLAN OFDM transmitter with digital filters, in the Proceedings of Mobimedia'2007, Nafpaktos, Greece, Aug. 2007.
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2006
JOURNALS
-- K. Masselos, Y. Andreopoulos and T. Stouraitis, Performance comparison of two-dimensional discrete wavelet transform computation schedules on a VLIW digital signal processor, IEE Proceedings Vision, Image & Signal Processing, vol. 153, no. 2, pp. 173-180, April 2006.
CONFERENCES
-- K. Karagianni, V. Paliouras, T. Giannopoulos, Low-power saturated arithmetic and its application in VLSI architectures for OFDM modems, Proceedings of the IEEE Workshop on Signal Processing Systems Design and Implementation, SIPS'2006, pp. 200-204, Oct. 2006.
-- S. Gidaros, V. Paliouras, Simplified criteria for early iterative decoding termination, Proceedings of the IEEE Workshop on Signal Processing Systems Design and Implementation, SIPS'2006, pp. 209-214, Oct. 2006.
-- T. Giannopoulos, V. Paliouras, A low-complexity PTS-based PAPR reduction technique for OFDM signals without transmission of side information, Proceedings of the IEEE Workshop on Signal Processing Systems Design and Implementation, SIPS'2006, pp. 434-439, Oct. 2006.
-- T. Giannopoulos, V. Paliouras, A novel technique for low-power D/A conversion based on PAPR reduction, Proceedings of the IEEE International Symposium on Circuits and Systems, ISCAS'2006, pp. 4999-5002, May 2006.
-- K. Masselos, Y. Andreopoulos, T. Stouraitis, Execution time comparison of lifting-based 2-D wavelet transform implementations on a VLIW DSP, in the Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS'2006, May 2006, Kos, Greece.
-- D. Schinianakis, A. Fournaris, A. Kakarountas, T. Stouraitis, An RNS architecture of an Fp elliptic curve point multiplier, in the Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS'2006, May 2006, Kos, Greece.
-- T. Giannopoulos, V. Paliouras, Novel efficient weighting factors for PTS-based PAPR reduction in low-power OFDM transmitters, EUSIPCO'2006, 2006.
-- Th. Giannopoulos, V. Paliouras, Low-power maximum magnitude computation for PAPR reduction in OFDM transmitters, PATMOS'2006, LNCS 4148, Springer, pp. 203-213, 2006.
EDITORIALS
-- V. Paliouras, T. Stouraitis, A.Ioinovici, Introduction, Advanced Signal Processing, Circuits, and System Design Techniques for Communications, pp. 1-2, May 2006.
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2005
JOURNALS
-- A. Briassouli, P. Tsakalides and T. Stouraitis, Hidden messages in heavy-tails: DCT-domain watermark detection using alpha-stable models, IEEE Transactions on Multimedia, vol. 7, No. 4, pp. 700-715, Aug. 2005.
-- D.F. Chiper, M.N.S. Swamy, M.O. Ahmad, and T. Stouraitis, Systolic algorithms and a memory-based design approach for a unified architecture for the computation of DCT/DST/IDCT/IDST, IEEE Transactions on Circuits and Systems-II, vol. 52, no. 6, pp. 1125-1137, June 2005.
CONFERENCES
-- V. Zygouris, K. Karagianni, T. Stouraitis, A Navier-Stokes processor for biomedical applications, in Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS'2005, Nov. 2005.
-- G. Glikiotis, V. Paliouras, A low-power termination criterion for iterative LDPC code decoders, in Proceedings of the IEEE Workshop on Signal Processing Systems Design and Implementation, pp. 122-127, Nov. 2005.
-- G. Glikiotis, V. Paliouras, A low-power termination criterion for iterative LDPC code decoders, in Proceedings of the IEEE Workshop on Signal Processing Systems Design and Implementation, pp. 122-127, Nov. 2005.
-- P. Vouzis, M.G. Arnold, V. Paliouras, Using CLNS for FFTs in OFDM demodulation of UWB receivers, in Proceedings of the IEEE International Symposium on Circuits and Systems, ISCAS'2005, vol. 4, pp. 3954-3957, May 2005.
-- T. Giannopoulos,V. Paliouras, Low-power VLSI architectures for OFDM transmitters based on PAPR reduction, in the Proceedings of Power and Timing Modeling, Optimization and Simulation, PATMOS'2005, pp. 177-186, Springer-Verlag, 2005.
-- K. Karagianni, V. Paliouras, Low-power aspects of nonlinear digital signal processing, in the Proceedings of Power and Timing Modeling, Optimization and Simulation, PATMOS'2005, pp. 518-527, Springer-Verlag, 2005.
EDITORIALS
-- T. Stouraitis, M. Bayoumi, V. Paliouras, Chairs' welcome message, in Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS'2005, Nov. 2005.
-- V. Paliouras, J. Vounckx, D. Veerkest, (editors), Integrated circuit and system design: power and timing modeling, optimization and simulation, 15th International Workshop, PATMOS'2005, Lecture Notes in Computer Science (LNCS 3728), Spinger Verlag, 2005.
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2004
JOURNALS
-- G. Dimitrakopoulos, V. Paliouras, A novel architecture and a systematic graph-based optimization methodology for modulo multiplication, IEEE Transactions on Circuits and Systems-I, vol. 51, no. 2, pp. 354-370 , Feb. 2004.
CONFERENCES
-- D.F. Chiper, M.N.S. Swamy, M.O. Ahmad, and T. Stouraitis, Systolic algorithms and a memory-based design approach for a unified architecture for the computation of DCT/DST/IDCT/IDST, IEEE Transactions on Circuits and Systems-II, vol. 52, no. 6, pp. 1125-1137, June 2005.
-- E. Fotopoulou, V. Paliouras, An efficient computational method and a VLSI architecture for digital filtering of CP-OFDM signals, in Proceedings of IEEE Global Telecommunications Conference, GLOBECOM'2004, vol. 4, pp. 2393-2397, Nov.-Dec. 2004.
-- T. Giannopoulos, V. Paliouras, An efficient architecture for peak-to-average power ratio reduction in OFDM systems in the presence of pulse-shaping filtering, in Proceedings of the IEEE International Symposium on Circuits and Systems, ISCAS'2004, vol. 4, pp. 85-88, May 2004.
-- S. Krommydas, V. Paliouras, Coefficient Compression for 8k FFT and the corresponding error model, in Proceedings of the IEEE International Symposium on Circuits and Systems, ISCAS'2004, vol. 4, pp. 89-92, May 2004.
-- P. Vouzis and V. Paliouras, Optimal logarithmic representation in terms of SNR behavior, in the Proceedings of Power and Timing Modeling, Optimization and Simulation, PATMOS'2004, pp. 760-769, Springer-Verlag, 2004.
EDITORIALS
-- E. Macii, V. Paliouras, O. Koufopavlou, (editors) Integrated circuit and system design: power and timing modeling, optimization and simulation, 14th International Workshop, PATMOS'2004, Lecture Notes in Computer Science (LNCS 3254), Spinger Verlag, 2004.
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2003
JOURNALS
-- K. Masselos, P. Merakos, S. Theoharis, T. Stouraitis, C.E. Goutis, Power efficient data path synthesis of sum-of-products computations, IEEE Transactions on Very Large Scale of Integration Systems, vol. 11, no. 3, pp. 446-450, June 2003.
CONFERENCES
-- K. Karagianni, V. Paliouras, Efficient third-order Volterra filter computation in the time domain, in Proceedings of 37th Asilomar Conference on Signals, Systems and Computers, vol. 2, pp. 2180-2184, Nov. 2003.
-- E. Fotopoulou, V. Paliouras, T. Stouraitis, A computational technique and a VLSI architecture for digital pulse shaping in OFDM modems, in Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS'2003, vol. 2, pp. 125-128, May 2003, Bangkok, Thailand.
-- P. Merakos, K. Masselos, S. Theoharis, T. Stouraitis, C.E. Goutis, Optimization techniques for reducing global bus switching activity in realizations of sum-of-products computations in DSP systems, IEE Proceedings on Circuits Systems and Devices, vol. 150, no. 1, pp. 16-26, Feb. 2003.
-- Uwe Meyer-Baese and T. Stouraitis, A new power-of-2 RNS scaling scheme for cell-based IC design , IEEE Transactions on VLSI Systems, vol. 11, no. 2, pp. 1-5, April 2003.
 -- I. Kouretas, V. Paliouras, High-radix redundant circuits for RNS modulo rn-1, rn, or rn + 1, in Proceedings of the IEEE International Symposium on Circuits and Systems, ISCAS'2003, vol. 5, 2003.
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2002
JOURNALS
-- K. Masselos, S. Theoharis, P. Merakos, T. Stouraitis, C.E. Goutis, Memory accesses reordering for interconnect power reduction in sum-of-products computations, IEEE Transactions on Signal Processing, vol. 50, No. 11, pp. 2889-2899, Nov. 2002.
-- D. F. Chiper, M.N.S. Swamy, M.O. Ahmad, and T. Stouraitis, A systolic array architecture for the discrete sine transform, IEEE Transactions on Signal Processing, vol. 50, no. 9, pp. 2347-2354, Sept. 2002.
-- V. Paliouras, T. Stouraitis, Designing CMOS circuits for low power, pp. 97-116, ESDLPD Book Series, Kluwer Academic Publishers, 2002.
CONFERENCES
-- V. Paliouras, A. Skavantzos, Novel forward and inverse PRNS converters of reduced computational complexity, in Proceedings of 36th Asilomar Conference on Signals, Systems and Computers, vol. 2, pp. 1603-1607, Nov. 2002.
 -- I. Kouretas, V. Paliouras, High-radix modulo rn - 1 multipliers and adders, in Proceedings of the 9th International Conference on Electronics, Circuits and Systems, ICECS'2002, vol. 2, pp. 561-564, Sept. 2002.
-- G. Dimitrakopoulos, V. Paliouras, Graph-based optimization for a CSD-enhanced RNS multiplier, in Proceedings of 45th Midwest Symposium on Circuits and Systems, MWSCAS'2002, vol. 3, pp. 648-651, Aug. 2002.
-- K. Karagianni, T. Stouraitis, VLSI architectures for the implementation of the Wigner distribution, in Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS'2002, Scottsdale, Arizona, May 2002.
-- G. Synevriotis, T. Stouraitis, A novel list-scheduling algorithm for the low-energy program execution, in Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS'2002, Scottsdale, Arizona, May 2002.
-- V. Paliouras, A. Skavantzos, T. Stouraitis, Low power convolvers using the polynomial residue number system, in Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS'2002, vol. 2, pp. 748-751, Scottsdale, Arizona , May 2002.
-- V. Paliouras, Optimization of LNS operations for embedded signal processing applications, in Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS'2002, vol. 2, pp. 744-747, Scottsdale, Arizona , May 2002.
-- V. Paliouras, A. Skavantzos, T. Stouraitis, Multi-voltage low power convolvers using the polynomial residue number system, in Proceedings of 12th Great Lakes Symposium on VLSI, April 18-20, 2002, New York City.
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2001
JOURNALS
-- V. Paliouras, K. Karagianni, and T. Stouraitis, A low-complexity combinatorial RNS multiplier, IEEE Transactions on Circuits and Systems-II, vol 48, no. 7, pp. 675-683, July 2001.
-- T. Stouraitis and V. Paliouras, Considering the alternatives in low-power design , IEEE Circuits and Devices Magazine, pp. 23-29, July 2001
-- K. Karagianni , V. Paliouras, G. Diamantakos, T. Stouraitis, Operation saving VLSI architecture s for 3-D geometrical transformations , IEEE Transactions on Computers,vol. 50, no. 6, pp. 609 -622, June 2001.
CONFERENCES
-- Y. Andreopoulos, N. Zervas, Lafruit, P. Schelkens, T. Stouraitis, C. Goutis, and J. Cornelis, A Local Wavelet transform implementation versus an optimal row-column algorithm for the 2D multilevel decomposition, in Proceedings of 2001 IEEE International Conference on Image Processing, ICIP'2001, Thessaloniki, Greece, October 7-10, 2001.
-- V. Paliouras, J. Dagres, P. Tsakalides, and T. Stouraitis, VLSI architectures for blind equalization based on fractional-order statistics, in Proceedings of 8thInternational Conference on Electronics, Circuits, and Systems, ICECS'2001, Malta, September 2001.
-- V. Paliouras and T. Stouraitis, Low-power properties of the logarithmic number system, in Proceedings of 15th IEEE Symposium on Computer Arithmetic, Vail, Colorado, 11-13 June 2001.
-- Y. Andreopoulos, P. Schelkens, T. Stouraitis, J. Cornelis, Implementing efficiently a Wavelet transform, a roadmap, in Proceedings of the 8 th International Workshop on Systems, Signals and Image Processing, IWSSIP'2001, Special session on "The role of wavelets in modern multimedia standards, Bucharest, Romania, June 2001.
-- V. Paliouras and T. Stouraitis, Signal activity and power consumption reduction using the logarithmic number system, in Proceedings of IEEE International Symposium on Circuits and Systems 2001. Sydney, May 2001.
-- K. Karagianni, T. Stouraitis, A vector processor for 3-D geometrical transformations, in Proceedings of IEEE International Symposium on Circuits and Systems 2001. Sydney, May 2001.
-- Y. Andreopoulos, P. Schelkens, J. Cornellis, N. Zervas, C. Goutis, T. Stouraitis, A Wavelet-tree image coding system with efficient memory utilization , in Proceedings of 2001 IEEE International Conference on Acoustics Speech and Signal Processing, ICASSP'2001, Salt Lake City, Utah, USA, May, 2001.
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2000
JOURNALS
-- V. Paliouras and T. Stouraitis, Novel high-radix residue number system processors , IEEE Transactions on Circuits and Systems, Part II, Vol. 47, No. 10, pp. 1059-1073, Oct. 2000.
-- V. Paliouras, K. Karagianni , T. Stouraitis, A VLSI architecture for fast and accurate floating-point sine/cosine evaluation, IEEE Transactions on Circuits and Systems II, Vol. 47, No. 5, pp. 441-451, May 2000.
-- K. Masselos, P. Merakos, T. Stouraitis, C. E. Goutis, Low power architectures for digital signal processing journal of systems architecture, Elsevier Publishers, vol 46, no. 7, pp. 551-571, April 2000.
CONFERENCES
-- V. Paliouras and T. Stouraitis, High-radix residue number system forward and inverse converters, 7th IEEE International Conference on Electronics, Circuits & Systems, ICECS'2000, Dec. 2000, Kaslik, Lebanon.
-- Masselos K., Karayiannis Y.A. Andreopoulos, I. Stouraitis, T, Development of a power efficient image coding algorithm based on integer Wavelet transform, 7th IEEE International Conference on Electronics, Circuits & Systems, ICECS'2000, Dec. 2000 Kaslik, Lebanon.
-- T. Stouraitis, The impact of arithmetic in lowering the chip energy consumption, NORCHIP'2000, Turku, Finland Nov. 2000.
-- V. Paliouras, K. Karagianni, and T. Stouraitis, A low-complexity RNS multiplier, in Proceedings of Signal Processing Systems, SiPS'2000, Lafayette, USA, Oct. 2000.
-- V. Paliouras and T . Stouraitis, Logarithmic number system for low-power arithmetic, in Proceedings of PATMOS 2000, Sep. 2000, LNCS 1918, pp. 285-294, Springer-Verlag, 2000.
-- K. Masselos, S. Theoharis, P.K. Merakos, T. Stouraitis and C. E. Goutis, Low power synthesis of sum-of-products computation, ACM/IEEE International Symposium on Low Power Electronic Design, ISLPED'2000, July 2000, Portofino, Italy.
-- I. Andreopoulos, Y. A. Karayiannis, T. Stouraitis, A hybrid image compression algorithm based on fractal coding and Wavelet transform. In proceedings of 2000 IEEE International Symposium on Circuits and Systems, ISCAS'2000, Geneva, May 2000.
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